Back to program overviev

Keynote 1: Michael J. Flynn    Dataflow Supercomputing     (Talk)

Keynote 2: Steve Trimberger    Beyond Moore. Beyond Programmable Logic.     (Talk)

Keynote 3: Deshanand Singh    Compiling OpenCL to FPGAs     (Talk)

Keynote 4: Steve Teig    Going beyond the FPGA with Spacetime     (Talk)

Plenary: Espen Tallaksen    FPGA development in Norwegian Industry     (Talk)

W1ASide-Channel Security                       Back to program overviev
  Session chair: Lionel Torres
W1A1 PresentationDetecting Power Attacks on Reconfigurable Hardware
Adrien Le Masle and Wayne Luk
W1A2 PresentationEfficient and Side-Channel-Secure Block Cipher Implementation with Custom Instructions on FPGA
Suvarna Mane, Mostafa Taha and Patrick Schaumont
W1BSoftware-Defined Radio
  Session chair: Lesley Shannon
W1B1 PresentationCRUSH: Cognitive Radio Universal Software Hardware
George Eichinger, Miriam Leeser and Kaushik Chowdhury
W1B2 PresentationData Coding Functions for Software Defined Radios Implemented on R3TOS
Raúl Torrego, Iñaki Val, Eñaut Muxika, Xabier Iturbe and Khaled Benkrid
W1CRapid Prototyping
  Session chair: Ron Sass
W1C1 PresentationEmPower: FPGA Based Rapid Prototyping of Dynamic Power Management Algorithms for Multi-Processor Systems on Chip
Chirag Ravishankar, Sundaram Ananthanarayan, Siddharth Garg and Andrew Kennings
W1C2 PresentationLimitations of Incremental Signal-Tracing for FPGA Debug
Extra resourcesEddie Hung and Steven J. E. Wilton
W2ASecure Reconfiguration
  Session chair: Nele Mentens
W2A1 PresentationSecURe DPR: Secure Update Preventing Replay Attacks for Dynamic Partial Reconfiguration
Florian Devic, Lionel Torres, Jérémie Crenne, Benoît Badrignans and Pascal Benoît
W2A2 PresentationFPGAs for Trusted Cloud Computing
Ken Eguro and Ramarathnam Venkatesan
W2BSoftware-Defined Radio
  Session chair: Christian Hochberger
W2B1 PresentationUsing DSP Block Pre-Adders in Pipeline SDF FFT Implementations in Contemporary FPGAs
Carl Ingemarsson, Petter Källström and Oscar Gustaffson
W2B2 PresentationEfficient DVB-T2 Decoding Accelerator Design by Time-Multiplexing FPGA Resources
Michael Feilen, Matthias Ihmig, Christian Schwarzbauer and Walter Stechele
W2CFPGA Routing
  Session chair: Steve Wilton
W2C1 PresentationOn the Difficulty of Pin-to-Wire Routing in FPGAs
Niyati Shah and Jonathan Rose
W2C2 PresentationRouting Algorithms for FPGAs with Sparse Intra-Cluster Routing Crossbars
Yehdhih Ould Mohammed Moctar, Guy G. F. Lemieux and Philip Brisk
W3ABio-inspired Applications
  Session chair: Kyrre Glette
W3A1 PresentationParallel FPGA-Based All Pairs Shortest Paths for Sparse Networks: A Human Brain Connectome Case Study
Brahim Betkaoui, Yu Wang, David B. Thomas and Wayne Luk
W3A2 PresentationBio-Inspired Walking: a FPGA Multicore System for a Legged Robot
Michael Henrey, Sean Edmond, Lesley Shannon and Carlo Menon
W3A3 PresentationA Scalable FPGA-Based Design for Field Programmable Large-Scale Ion Channel Simulations
Graeme Coapes, Terrence Mak, Jun Wen Luo, Alex Yakovlev and Chi-Sang Poon
W3BFluid Flow Simulation
  Session chair: Yoshiki Yamaguchi
W3B1 PresentationScalability Analysis of Tightly-Coupled FPGA-Cluster for Lattice Boltzmann Computation
Yoshiaki Kono, Kentaro Sano and Satoru Yamamoto
W3B2 PresentationFPGA Based Acceleration of Computational Fluid Flow Simulation on Unstructured Mesh Geometry
Zoltán Nagy, Csaba Nemes, Antal Hiba, András Kiss, Árpád Csík and Péter Szolgay
W3B3 Presentation PPTXReconfigurable Out-of-Order Mechanism Generator for Unstructured Grid Computation in Computational Fluid Dynamics
Takayuki Akamine, Kenta Inakagata, Yasunori Osana, Naoyuki Fujita and Hideharu Amano
W3CFloorplanning and Placement
  Session chair: Marco Platzner
W3C1 Presentation PPTAnalytical Placement for Heterogeneous FPGAs
Marcel Gort and Jason H. Anderson
W3C2 PresentationProfiling FPGA Floor-Planning Effects on Timing Closure
Jaren Lamprecht and Brad Hutchings
W3C3 PresentationMulti-Kernel Floorplanning for Enhanced CGRAS
Aaron Wood, Adam Knight, Benjamin Ylvisaker and Scott Hauck
W4AApplications Using PR
  Session chair: Dirk Stroobandt
W4A1 Presentation PPTOptimising Explicit Finite Difference Option Pricing for Dynamic Constant Reconfiguration
Qiwei Jin, Tobias Becker, Wayne Luk and David Thomas
W4A2 PresentationExploiting Run-Time Reconfiguration in Stencil Computation
Xinyu Niu, Qiwei Jin, Wayne Luk, Qiang Liu and Oliver Pell
W4BHigh-Level Design
  Session chair: Joao Cardoso
W4B1 PresentationA Two Step Hardware Design Method Using Cλash
Rinse Wester, Christiaan Baaij and Jan Kuper
W4B2 PresentationConvey Vector Personalities – FPGA Acceleration with an OpenMP-Like Programming Effort?
Björn Meyer, Jörn Schumacher, Christian Plessl and Jens Förstner
W4CCAD Tools
  Session chair: Jonathan Rose
W4C1 PresentationImproving Memory Support in the VTR Flow
Andrew Somerville and Kenneth B. Kent
W4C2 PresentationVerification of Streaming Designs by Combining Symbolic Simulation and Equivalence Checking
Tim Todman and Wayne Luk
T1A Application Acceleration 1                       Back to program overviev
  Session chair: Stefan Wildermann
T1A1 PresentationHardware Implementation of MRF MAP Inference on an FPGA Platform
Jungwook Choi and Rob A. Rutenbar
T1A2 PresentationCAAD BLASTP 2.0: NCBI BLASTP Accelerated with Pipelined Filters
Atabak Mahram and Martin C. Herbordt
T1BMulti Cores on FPGAs
  Session chair: Christian Plessl
T1B1 PresentationPolyBlaze: From One to Many. Bringing the Microblaze Into the Multicore Era with Linux SMP Support
Eric Matthews, Lesley Shannon and Alexandra Fedorova
T1B2 PresentationAutomating the Design of MLUT MPSoPC FPGAs in the Cloud
David Andrews, Miaoqing Huang, Azad Fakhari, Eugene Cartwright, Sen Ma, Christina Smith and Jason Agron
T1CIndustry Session 1
  Session chair: Heiko Kalte
T2AApplication Acceleration 2
  Session chair: Dionisios Pnevmatikatos
T2A1 PresentationA Scalable Complex Event Processing Framework for Combination of SQL-Based Continuous Queries and C/C++ Functions
Takashi Takenaka, Masamichi Takagi and Hiroaki Inoue
T2A2 PresentationHardware Implementation of Motion Blur Removal
Thusitha N. Chandrapala, Amila P. Cabral, Thilina S. Ambagahawaththa, Sapumal Ahangama and Jayathu G. Samarawickrama
T2BFloating Point Arithmetic
  Session chair: Miriam Leeser
T2B1 PresentationCorrectly Rounded Floating-Point Division for DSP-Enabled FPGAs
Bogdan Pasca
T2B2 PresentationReduced Complexity Single and Multiple Constant Multiplication in Floating Point Precision
Martin Kumm, Katharina Liebisch and Peter Zipf
T2CIndustry Session 2
  Session chair: Ken Eguro
T3ACommunications and Networking
  Session chair: Kyle Rupnow
T3A1 PresentationFPGA-Based Design and Implementation of a Multi-Gbps LDPC Decoder
Alexios Balatsoukas-Stimming and Apostolos Dollas
T3A2 PresentationOptimizing Packet Lookup in Time and Space on FPGA
Thilan Ganegedara, Viktor Prasanna and Gordon Brebner
T3A3 PresentationArchitecture and FPGA Implementation of a 10.7 Gbit/s OTN Regenerator for Optical Communication Systems
Rodrigo Bernardo, Luis R. Monte, Eduardo Mobilon, Arley H. Salvador, Carolina G. Neves, Cleber A. Nakandakare, Ronaldo F. da Silva, Daniele R. da Silva, Luis P. F. de Barros and Valentino Corso
T3BReliability and Fault-Tolerance
  Session chair: Peter Cheung
T3B1 PresentationHigh-Level Aging Estimation for FPGA-Mapped Designs
Abdulazim Amouri and Mehdi Tahoori
T3B2 PresentationTolerating Multiple Faults with Proximate Manifestations in FPGA-Based Critical Designs for Harsh Environments
Jaime Espinosa, David de Andrés, Juan Carlos Ruiz and Pedro Gil
T3B3 PresentationOverhead and Reliability Analysis of Algorithm-Based Fault Tolerance in FPGA Systems
Adam Jacobs, Grzegorz Cieslewski and Alan D. George
T3CCAD for Partial Reconfiguration
  Session chair: Suhaib Fahmy
T3C1 PresentationAutomatically Exploiting Regularity in Applications to Reduce Reconfiguration Memory Requirements
Fatma Abouelella, Karel Bruneel and Dirk Stroobandt
T3C2 PresentationMapping Logic to Reconfigurable FPGA Routing
Karel Heyse, Karel Bruneel and Dirk Stroobandt
T3C3 PresentationMaximizing the Reuse of Routing Resources in a Reconfiguration-Aware Connection Router
Elias Vansteenkiste, Karel Bruneel and Dirk Stroobandt
T4AFeature extraction and Classification
  Session chair: David Andrews
T4A1 PresentationRandom Decision Tree Body Part Recognition Using FPGAs
Jason Oberg, Ken Eguro, Ray Bittner and Alessandro Forin
T4A2 PresentationAcceleration of Distance-to-Default with Hardware-Software Co-Design
Izaan Allugundu, Pranay Puranik, Yat Piu Lo and Akash Kumar
T4A3 PresentationAn Efficient Hardware Architecture of the Optimised SIFT Descriptor Generation
Wenjuan Deng, Yiqun Zhu, Hao Feng and Zhiguo Jiang
T4BReconfigurable Architectures
  Session chair: Brad Hutchings Brigham Young University
T4B1 PresentationAdding Dataflow-Driven Execution Control to a Coarse-Grained Reconfigurable Array
Robin Panda, Carl Ebeling and Scott Hauck
T4B2 PresentationA 16-Configuration-Context Robust Optically Reconfigurable Gate Array with a Reconfiguration Speed Adjustment Function
Takashi Yoza and Minoru Watanabe
T4B3 PresentationNon-Volatile 3D Stacking RRAM-Based FPGA
Yi-Chung Chen, Wenhua Wang, Hai Li and Wei Zhang
T4CPhysical Parameters Sensing
  Session chair: Katherine Compton
T4C1 PresentationIntra-Chip Physical Parameter Sensor for FPGAs Using Flip-Flop Metastability
Ghaith Tarawneh, Terrence Mak and Alex Yakovlev
T4C2 PresentationA Novel Microprocessor-Intrinsic Physical Unclonable Function
Abhranil Maiti and Patrick Schaumont
T4C3 PresentationFPGA Based Key Generation Technique for Anti-Counterfeiting Methods Using Physically Unclonable Functions and Artificial Intelligence
Swetha Pappala, Mohammed Niamat and Weiqing Sun
F1AOn-FPGA Communication                       Back to program overviev
  Session chair: Paul Chow
F1A1 PresentationDESA: Distributed Elastic Switch Architecture for Efficient Networks-on-FPGAs
Antoni Roca, Jose Flich and Giorgos Dimitrakopoulos
F1A2 PresentationAn Area-Efficient Partially Reconfigurable Crossbar Switch with Low Reconfiguration Delay
Chin Hau Hoo and Akash Kumar
F1BComputer Vision 1
  Session chair: Kentaro Sano
F1B1 PresentationAn Acceleration of a Graph Cut Segmentation With FPGA
Daichi Kobori and Tsutomu Maruyama
F1B2 PresentationAn FPGA Acceleration of a Level Set Segmentation Method
Haruhisa Tsuyama and Tsutomu Maruyama
F1CIP cores and IP integration
  Session chair: Andreas Koch
F1C1 PresentationA High Performance, Open Source SATA2 Core
Ashwin A. Mendon, Bin Huang and Ron Sass
F1C2 PresentationIP-XACT Extensions for IP Interoperability Guarantees and Software Model Generation
Thomas P. Perry, Richard L. Walke, Rob Payne, Stefan Petko and Khaled Benkrid
F2AApplication Acceleration 3
  Session chair: Koen Bertels
F2A1 PresentationK-Means Implementation on FPGA for High-Dimensional Data Using Triangle Inequality
Zhongduo Lin, Charles Lo and Paul Chow
F2A2 PresentationEnhancing Performance of Tall-Skinny QR factorization Using FPGAs
Abid Raque, Nachiket Kapre and George A. Constantinides
F2BComputer Vision
  Session chair: Apostolos Dollas
F2B1 PresentationReal-Time Corner and Polygon Detection System on FPGA
Chunmeng Bi and Tsutomu Maruyama
F2B2 PresentationDeep-Pipelined FPGA Implementation of Ellipse Estimation for Eye Tracking
Keisuke Dohi, Yuma Hatanaka, Kazuhiro Negi, Yuichiro Shibata and Kiyoshi Oguri
  Session chair: Jason Anderson
F2C1 PresentationA Benign Hardware Trojan on FPGA-Based Embedded Systems
Jason X. Zheng, Ethan Chen and Miodrag Potkonjak
F2C2 PresentationBreaking the GSM A5/1 Cryptography Algorithm with Rainbow Tables and High-End FPGAs
Maria Kalenderi, Dionisios Pnevmatikatos, Ioannis Papaefstathiou and Charalampos Manifavas
Back to program overviev
PHDPHD Forum (Wednesday)
PHD1 PresentationA Resiliency-Aware Scheduling Approach for FPGA Configuration: Preliminary Results
Jeremy Abramson and Pedro C. Diniz
PHD2 PresentationPower/Performance Optimization in FPGA-Based Asymmetric Multi-Core Systems
Bruno De Abreu Silva and Vanderlei Bonato
PHD3 PresentationThermal-Aware Partitioning for 3D FPGAs
Krishna Chaitanya Nunna, Farhad Mehdipour and Kazuaki Murakami
PHD4 PresentationReconfigurable Multi-Processor Architecture For Streaming Applications
Leyla S. Ghazanfari, Roberto Airoldi, Jari Nurmi and Tapani Ahonen
PHD5 PresentationNoC-AXI Interface for FPGA-based MPSoc Platforms
Marco Ramirez, Masoud Daneshtalab, Juha Plosila and Pasi Liljeberg
PHD6 PresentationModeling of Dynamic Reconfigurable Systems with Haskell
Bahram N.Uchevler and Kjetil Svarstad
PHD7 PresentationStimulation Board for Automated Verification of Touchscreen-based Devices
Ivan Kastelan, Vladimir Marinkovic, Radomir Dzakula, Nikola Vranic and Vukota Pekovic
PHD8 PresentationHigh Level Structural Description of Streaming Applications
Anja Niedermeier, Jan Kuper and Gerard J.M. Smit
PHD9 PresentationAmbient Hardware and the Case for Transcoding Media Streams
Milica Orlandi and Kjetil Svarstad
PHD10 PresentationCombining Data and Computation Transformations for Fine-Grain Reconfigurable Architectures
Cristiano B. Oliveira and Eduardo Marques
PHD11 PresentationImplementation ans Outcomes of FPGA-based System Design in Mongolian Education
D. Erdenechimeg, Ts. Sugir Computer Engineering Department CSMS - MUST, Mongolia
F. Philipp and M. Glesner Microelectronic Systems Research Group, TU Darmstadt, Germany
Back to program overviev
WPPoster Session 1 (Wednesday)             Back to program overviev
WP01 PresentationCaaS: Core as a Service Realizing Hardware Sercices on Reconfigurable MPSoCs
Chao Wang, Xi Li, Junneng Zhang, Peng Chen and XuehaiZhou
WP02 PresentationHardware Acceleration and Data-Utility Improvement for Low-Latency Privacy Preserving Mechanism
Junichi Sawada and Hiroaki Nishi
WP03 PresentationDataflow Graph Partitioning for High Level Synthesis
Sharad Sinha and Thambipillai Srikanthan
WP04 PresentationA Fast and High Quality Stereo Matching Algorithm on FPGA
Minxi Jin and Tsutomu Maruyama
WP05 PresentationAn FPGA Aligner for Short Read Mapping
Yupeng Chen, Bertil Schmidt and Douglas L. Maksell
WP06 PresentationRaising the Abstraction Level of HDL for Control-Dominant Applications
Marc-Andre Daigneault and Jean Pierre David
WP07 PresentationA Two-Stage Variation-Aware Placement Method for FPGAs Exploiting Variation Maps Classification
Zhenyu Guan, Justin S. J. Wong, Sumanta Chaudhuri, George Constantinides and Peter Y. K. Cheung
WP08 PresentationSpeedy Bus Mastering PCI Express
Ray Bittner
WP09 PresentationAdaptive Sequential Monte Carlo Approach for Real-Time Applications
Thomas C.P. Chau, Wayne Luk, Peter Y.K. Cheung, Alison Eele and Jan Maciejowski
WP10 PresentationFrom OpenCL to High-Performance Hardware on FPGAs
Tomasz S. Czajkowski, Utku Aydonat, Dmitry Denisenko, John Freeman, Michael Kinsner, David Neto, Jason Wong, Peter Yiannacouras and Deshanand P. Singh
WP11 PresentationA Framework for Open Tiled Manycore System-on-Chip
Stefan Wallentowitz, Andreas Lankes, Aurang Zaib, Thomas Wild and Andreas Herkersdorf
WP12 PresentationFault Detection and Avoidance of FPGA in Various Granularities
Kazuki Inoue, Yuki Nishitani, Motoki Amagasaki, Masahiro Iida, Morihiro Kuga and Toshinori Sueyoshi
WP13 PresentationCMA-Cube: a Scalable Reconfigurable Accelerator with 3-D Wireless Inductive Coupling Interconnect
Yusuke Koizumi, Eiichi Sasaki, Hideharu Amano, Hiroki Matsutani, Yasuhiro Take, Tadahiro Kuroda, Ryuichi Sakamoto, Mitaro Namiki, Kimiyoshi Usami, Masaaki Kondo, and Hiroshi Nakamura
WP14 PresentationImplementation Techniques for Evolvable HW Systems: Virtual vs. Dynamic Reconfiguration
Ruben Salvador, Andres Otero, Javier Mora, Eduardo de la Torre, Teresa Riesgo and Lukáš Sekanina
WP15 PresentationDevelopment of an FPGA-based Real-Time P300 Speller
Kanav Khurana, Pooja Gupta, Rajesh C. Panicker and Akash Kumar
WP16 PresentationInfluence of Operating Conditions on Ring Oscillator-Based Entropy Sources in FPGAs
Christian Hochberger, Changgong Li, Michael Raitza and Markus Vogt
WP17 PresentationExploration of Ring Oscillator Design Space for Temperature Measurements on FPGAs
Christoph Ruething, Andreas Agne, Markus Happe and Christian Plessl
WP18 PresentationExtending BORPH for Shared Memory Reconfigurable Computers
Xun Changqing, Wen Mei, Wu Nan, Zhang Chunyuan and Hayden Kwok-Hay So
WP19 PresentationAutomatic Generation of Application-Specific Accelerators for FPGAs from Python Loop Nests
David Shefeld, Michael Anderson and Kurt Keutzer
WP20 PresentationPPMC : Hardware Scheduling and Memory Management Support for Multi Accelerators
Tassadaq Hussain, Miquel Pericàs, Nacho Navarro and Eduard Ayguadé
WP21 PresentationPerformance Analysis of Fully-Adaptable CRC Accelerators on an FPGA
Amila Akagic and Hideharu Amano
TPPoster Session 2 (Thursday)             Back to program overviev
TP01 PresentationArea Estimation of Look-Up Table Based Fixed-Point Computations on the Example of a Real-Time High Dynamic Range Imaging System
Michael Kunz, Martin Kumm, Martin Heide and Peter Zipf
TP02 PresentationDynamic Multiobjective Optimization Management of the Energy-Performance-Accuracy Space for Separable 2-D Complex Filters
Daniel Llamocca, Cesar Carranza and Marios Pattichis
TP03 PresentationHCM: An Abstraction Layer for Seamless Programming of DPR FPGA
Yan Xu, Olivier Muller, Pierre-Henri Horrein and Frédéric Pétrot
TP04 PresentationEarly Performance Estimation of Image Compression Methods on Soft Processors
Adam Powell, Christos-S. Bouganis and Peter Y.K. Cheung
TP05 PresentationSliding Block Viterbi Decoders in FPGA
Mário Véstias, Horácio Neto and Helena Sarmento
TP06 PresentationDynamic Query Switching for Complex Event Processing on FPGAs
Masamichi Takagi, Takashi Takenaka and Hiroaki Inoue
TP07 PresentationDual-Core Motion Estimation Processor
Joaquín Olivares and José M. Palomares
TP08 PresentationOn the Automatic Integration of Hardware Accelerators into FPGA-Based Embedded Systems
Christian Pilato, Andrea Cazzaniga, Gianluca Durelli, Andres Otero, Donatella Sciuto and Marco D. Santambrogio
TP09 PresentationDesign of a Novel Quantum-Dot Cellular Automata Field Programmable Gate Array
Hemant Balijepalli and Mohammed Niamat
TP10 PresentationA Predictive Delay Fault Avoidance Scheme for Coarse-Grained Reconfigurable Architecture
Toshihiro Kameda, Hiroaki Konoura, Dawood Alnajjar, Yukio Mitsuyama, Masanori Hashimoto and Takao Onoye
TP11 PresentationDWARV 2.0: A CoSy-based C-to-VHDL Hardware Compiler
Razvan Nane, Vlad-Mihai Sima, Bryan Olivier, Roel Meeuws, Yana Yankova and Koen Bertels
TP12 PresentationLow Area Memory-Free FPGA Implementation of the AES Algorithm
Junfeng Chu and Mohammed Benaissa
TP13 PresentationAn Adaptive FPGA Implementation of Multi-Core K-Nearest Neighbour Ensemble Classifier Using Dynamic Partial Reconfiguration
Hanaa Hussain, Khaled Benkrid, Chuan Hong and Huseyin Seker
TP14 PresentationFast Digital Rendering for Special Effects
Sam Collinson and John Morris
TP15 PresentationDesign and Utilization of an FPGA Cluster to Implement a Digital Wireless Channel Emulator
Scott Buscemi and Ron Sass
TP16 PresentationWire-Speed Verification Schemes for HW/SW Design of 10-Gbit/s-Class Large-Scale NW SoC Using Multiple FPGAs
Kazuhiko Terada, Hiroyuki Uzawa, Namiko Ikeda, Satoshi Shigematsu, Nobuyuki Tanaka and Masami Urano
TP17 PresentationA New Self-Adapting Architecture for Feature Detection
Paulo Da Cunha Possa, Sidi Ahmed Mahmoudi, Naim Harb and Carlos Valderrama
TP18 PresentationCustom Instructions with Local Memory Elements Without Expensive DMA Transfers
Alok Prakash, Christopher T. Clarke and Thambipillai Srikanthan
TP19 PresentationDual MicroBlaze Rekeying Processor for Group Key Management
José M. Granado-Criado, Miguel A. Vega-Rodriguez, Juan M. Sanchez-Perez and Juan A. Gomez-Pulido
TP20 PresentationLightweight Reconfiguration Security Services for AXI-Based MPSoCs
Pascal Cotret, Guy Gogniat, Jean-Philippe Diguet and Jérémie Crenne
TP21 PresentationExamination of the Concept of a Row-Column Separated Median Filter
D. Wang, C. T. Clarke and A. N. Evans
FPPoster Session 3 (Friday)             Back to program overviev
FP01 PresentationOn Reconfigurable Fabrics and Generic Side-Channel Countermeasures
Rob Beat, Philipp Grabher, Dan Page, Stafan Tillich and Marcin Wójcik
FP02 PresentationHardware Implementation of Stereo Correspondence Algorithm for the ExoMars Mission
G. Lentaris, D. Diamantopoulos, K. Siozios, D. Soudris and M. Avilés Rodriglvarez
FP03 PresentationDesign Space Exploration for Automatically Generated Cryptographic Hardware Using Functional Languages
Davy Wolfs , Kris Aerts and Nele Mentens
FP04 PresentationFast and Accurate Single Bit Error Injection into SRAM Based FPGAs
U. Kretzschmar, A. Astarloa, J. Jiménez, M. Garay and J. Del Ser
FP05 Presentation(GECO)²: A Graphical Tool for the Generation of Configuration Bitstreams for a Smart Sensor Interface Based on a Coarse-Grained Dynamically Reconfigurable Architecture
François Philipp and Manfred Glesner
FP06 PresentationDesign and Implementation of Fault-Tolerant Soft Processors on FPGAs
Chuan Hong, Khaled Benkrid, Xabier Iturbe and Ali Ebrahim
FP07 PresentationTowards GCC-Based Automatic Soft-Core Customization
Gerald Hempel, Christian Hochberger and Michael Raitza
FP08 PresentationAn Energy-Efficient Hardware Accelerator for Robust Header Compression in LTE-Advanced Terminals
Shadi Traboulsi, Wenlong Zhang, Daivd Szczesny, Anas Showk and Attila Bilgic
FP09 PresentationExploring the Latency-Resource Trade-off for the Discrete Fourier Transform on the FPGA
Gordon Inggs, David Thomas and Simon Winberg
FP10 PresentationiTester: A FPGA Based High Performance Traffic Replay Tool
Fuxing Zhang, Yingke Xie, Junjie Liu, Layong Luo, Qingsong Ning and Xiaolong Wu
FP11 PresentationModeling and Synthesis of a Dynamic and Partial Reconfiguration Controller
S. Guillet, F. de Lamotte, N. Le Griguer, É Rutten, J.-P. Diguet, G. Gogniat
FP12 PresentationAn Open-Source Design and Validation Platform for Reconfigurable Systems
Alessandra Bonetto, Andrea Cazzaniga, Gianluca Durelli, Christian Pilato, Donatella Sciuto and Marco D. Santambrogio
FP13 PresentationFloating Point HOG Implementation for Real-Time Multiple Object Detection
Mateusz Komorkiewicz, Maciej Kluczewski and Marek Gorgon
FP14 PresentationRuntime Reconfigurable DSP Unit Using One's Complement and Minimum Signed Digit
Travis Manderson and Laurence Turner
FP15 PresentationA High Performance and Low Energy Intra Prediction Hardware for High Efficiency Video Coding
Ercan Kalali, Yusuf Adibelli and Ilker Hamzaoglu
FP16 PresentationHigh-Level Linear Projection Circuit Design Optimization Framework for FPGAs Under Over-Clocking
Rui Policarpo Duarte and Christos-Savvas Bouganis
FP17 PresentationEvaluating the Efficiency of DSP Block Synthesis Inference from Flow Graphs
Bajaj Ronak and Suhaib A. Fahmy
FP18 PresentationSystem#: High-Level Synthesis of Physical Simulations for FPGA-Based Real-Time Execution
Christian Köllner, Nico Adler and Klaus Müller-Glaser
FP19 PresentationBIL: A Tool-Chain for Bitstream Reverse-Engineering
Florian Benz, André Seffrin and Sorin A. Huss
FP20 PresentationA Region Merging Approach for Image Segmentation on FPGA
Dang Ba Khac Trieu and Tsutomu Maruyama
FP21 PresentationOn Measurement of Impact of the Metallization and FPGA Design to the Changes of Slice Parameters and Generation of Delay Faults
Petr Pfeifer and Zdenek Pliva
Back to program overviev

Research Council of Norway logo City of Oslo logo  Microsemi logo  Xilinx logo  Altera logo Silica logo Sigasi logo Maxeler logo Synective logo CSIR logo Tabula logo CosReCos logo