Program Talk from: Philippe Faes (Sigasi)  Magnus Peterson (Synective)  Jaco Naude (CSIR) 

Oliver Pell (Maxeler)
Dataflow programming with MaxCompiler

Abstract

Pipelined dataflow architectures are highly efficient at executing complex computation on large datasets. In this talk we will describe the MaxCompiler dataflow development model, discuss some of the characteristics of dataflow programs and show how some example code patterns can be mapped into dataflow.

Philippe Faes (Sigasi)
Type-time compilation in industry and in education

Abstract

Software engineers have long used advanced integrated development tools (IDE) for their work. A principal feature of those IDE's is that code can be compiled while the engineer is typing, giving him instant feedback. This talk expands on the value of type-time compilation for industry. And for education.

 

Magnus Peterson (Synective)
Partitioning ANSI C Between CPUs and FPGAs for Improved Throughput and Reduced Power

Abstract

FPGAs are carving out a niche as CPU offload processors, squeezing more performance out of the same footprint, with equal or less power. Approximately 80% of algorithms are developed in ANSI C so the IP is there, if it can be easily split and portions routed to hardware. If we can work with ANSI C throughout the whole process, for both the CPU part and the FPGA part of the algorithm, we can verify the complete solution fully on a CPU and then in a later step find the most efficient partitioning between the CPU and the FPGA, without changing any code. The design can also be easily be migrated to newer FPGAs in a given brand, or to another FPGA brands. This short presentation covers how ImpulseC can be used to successfully profile, refactor and partition parts of a C design into an FPGA for overall system improvement, while maintaining the migrate-ability and equivalency of the code.

 

Magnus Peterson (Synective)
Solving "Big Data Analytics" Problems Using the Convey Heterogeneous Architecture

Abstract

Data-Intensive Computing is showing increasing importance in many fields like bioinformatics, data analytics and security. These graph related algorithms perform poorly on traditional computer architectures where their random data access patterns put a large burden on the memory subsystems, optimized for sequential access. This brief talk show how the Convey heterogeneous system can solve this category of problems with outstanding performance, minimal footprint and at ultra low power consumption.

 

Jaco Naude (CSIR)
Scineric Workspace - Structured File, Build and Package Management

Abstract

Scineric Workspace is a product which allows you to manage any arbitrary group of files and processes using a set of customizable rules. Focusing strongly on the processes involved in firmware development, it provides seamless integration with tools from multiple vendors allowing it to fit into your current workflow with little effort. It runs on top of IP-XACT based repositories, packing your designs in an industry standard format. We are re-imagining the way firmware engineers manage and share their designs, one step at a time.

 

Research Council of Norway logo City of Oslo logo  Microsemi logo  Xilinx logo  Altera logo Silica logo Sigasi logo Maxeler logo Synective logo CSIR logo Tabula logo CosReCos logo