Sinan Kaptanoglu (Microsemi)

Introduction to Flash FPGAs

Abstract

In this talk, I will give a very brief introduction to flash-FPGAs, with emphasis on FPGAs from Microsemi SOC division (formerly Actel.)

Non-volatile FPGAs based on flash cells as configuration memory have very unique and interesting properties and capabilities which make them the preferred FPGAs in specialized applications. These capabilities include full SEU immunity, very high bit-stream security, single chip solution live at power-up, and an order magnitude lower static power due to low leakage from the flash cells, and the ability to offer on-chip flash memory. To top it off, flash-FPGAs can pass rail-to-rail CMOS signals, and do not require level restoring pull-ups after every mux in the FPGA or require gate voltage pumping for the FPGA pass gates. Today, flash-FPGAs have become the preferred solution for all applications which require a high degree of reliability, as well applications where the user design security is highly valued. In addition, control based processor applications which require on-chip non-volatile memory usually rely on flash-FPGAs.

But the flash-FPGAs are not superior to SRAM based FPGAs in every aspect. For example flash-FPGAs are not at all suitable for dynamically reconfigurable computing. This is because the FPGA cannot be reprogrammed more than a few thousand times. A more important drawback is the fact that the embedded flash (more generally the embedded non-volatile memory) technology is at least a generation behind the standard CMOS, often two. Currently Microsemi SOC is sampling the 65nm flash-FPGAs.

Jan Anders Mathisen (SILICA)

The Xilinx All programmable SoC team up with High Level Synthesis (HLS) to provide the power of hardware acceleration to the software community

Abstract

With the introduction of the All Programmable SoC and new low-cost HLS tools, embedded computing with FPGA-enabled hardware co-processing is now going mainstream. New tools bring the design abstraction to a higher level, enabling developers to spend more time developing efficient algorithms in C/C++/SystemC rather than spending time on RTL implementation details. This may eventually bridge the gap between SW and HW developers.