Compiling OpenCL to FPGAs : A Standard and Portable Software Abstraction for System Design
Today's FPGAs have logic capacities that are steadily increasing. The FPGA is a large array of fine-grained programmable elements that can be configured in such a way to efficiently solve many complex problems. For many applications, FPGAs are a tremendously efficient computational fabric; however, the primary method of design entry for FPGAs is through Hardware Design Languages (HDLs) such as VHDL or Verilog. These languages model the FPGA at an extremely low level where the programmer is expected to understand cycle-accurate details of how data is moved and transformed through the FPGA. While this programming model is required to achieve the highest possible efficiency from FPGAs, it is akin to "assembly language" programming for processors. In this talk, we explore techniques that allow us to program FPGAs at a level of abstraction that is closer to traditional software-centric approaches using an emerging parallel language : OpenCL. The field of high level synthesis has evolved greatly in the last few decades; however, several fundamental parts were missing from the complete software abstraction of the FPGA. These include standard and portable methods of describing HW/SW codesign, memory hierarchy, data movement and control of parallelism. We believe that OpenCL addresses all of these issues and allows for highly efficient description of FPGA designs at a higher level of abstraction.
About Deshanand Singh
|Desh Singh is a Supervising Principal Engineer at Altera's Toronto Technology Center. Desh leads Altera's OpenCL-to-FPGA project and his charter is to develop high level design tools which allow designers to create applications for FPGAs with a higher level of productivity than traditionally possible. Previously, his group was responsible for a number of optimization algorithms in Altera's Quartus II CAD tool. These include Logic Synthesis, Line-level incremental compilation, Physical Synthesis, Metastability Analysis, and IP core optimizations. Desh holds a PhD from the University of Toronto in the area of timing closure techniques for high speed FPGA designs and has authored over 50 patents and publications on FPGA technology.|